Method for improved polysilicon etch dimensional control

ABSTRACT

Provided are methods of manufacturing integrated circuit that include a polysilicon etch process in which the wafer having an etch poly pattern is loaded into a reactor chamber and exposed to an activated etchant and, during the etch process, adjusting the temperature conditions within the reactor chamber to increase polymeric deposition on an upper surface of the wafer.

RELATED APPLICATIONS

This application is a divisional application of U.S. Pat. No.17,377,634, filed Jul. 16, 2021, the contents of which is incorporatedherein in its entirety.

BACKGROUND

Semiconductor devices are used in a variety of electronic applications,such as personal computers, cell phones, digital cameras, and otherelectronic equipment. Semiconductor devices are typically fabricated bysequentially depositing insulating or dielectric layers, conductivelayers, and semiconductor layers of material over a semiconductorsubstrate, and patterning the various material layers using lithographyto form circuit components and elements thereon. As the semiconductorindustry has progressed into nanometer technology process nodes inpursuit of higher device density, higher performance, and lower costs,challenges from both fabrication and design issues have resulted in thedevelopment of three-dimensional designs.

The semiconductor integrated circuit (IC) industry has experienced rapidgrowth. Technological advances in IC materials and design have producedgenerations of ICs with each generation having smaller and more complexcircuits than the previous generation. However, as the semiconductorindustry has progressed into nanometer technology process nodes inpursuit of higher device density, higher performance, and lower costs,the challenges in both fabrication and design of such devices hasresulted in the development of three-dimensional designs including, forexample, the fin field effect transistor (FinFET).

Although advantages of the FinFET include reducing short channel effectsand increasing current flow, the associated fabrication processescontinue to become more challenging as the feature sizes and thespacings between features continue to decrease.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1 is a cross-sectional view of an etching tool useful inmanufacturing a FinFET device structure according to some embodiments.

FIGS. 2A and 2B are cross-sectional views at an intermediate step in themanufacture of a FinFET device structure according to some embodiments.

FIGS. 3A and 3B are cross-sectional views at an intermediate step in themanufacture of a FinFET device structure according to some embodiments.

FIGS. 4A and 4B are cross-sectional views at an intermediate step in themanufacture of a FinFET device structure according to some embodiments.

FIG. 5 is a cross-sectional view of a FinFET device structure accordingto some embodiments.

FIG. 6 is a cross-sectional view of a FinFET device structure accordingto some embodiments with relevant dimensions marked.

FIG. 7 is a flowchart of a method of manufacturing a FinFET deviceaccording to some embodiments.

FIG. 8 is a schematic diagram of a system for manufacturing FinFETdevices according to some embodiments.

FIG. 9 is a flowchart of IC device design, manufacture, and programmingof IC devices according to some embodiments.

FIG. 10 is a chart of an etch process according to some embodiments.

DETAILED DESCRIPTION

This description of the exemplary embodiments is intended to be read inconnection with the accompanying drawings, which are to be consideredpart of the entire written description. The following disclosureprovides many different embodiments, or examples, for implementingdifferent features of the provided subject matter. The drawings are notto scale and the relative sizing and placement of structures have beenmodified for clarity rather than dimensional accuracy. Specific examplesof components, values, operations, materials, arrangements, or the like,are described below to simplify the present disclosure.

These are, of course, merely examples and are not intended to belimiting. Other components, values, operations, materials, arrangements,or the like, are contemplated. For example, the formation of a firstfeature over or on a second feature in the description that follows mayinclude embodiments in which the first and second features are formed indirect contact and may also include embodiments in which additionalfeatures may be formed between the first and second features, such thatthe first and second features may not be in direct contact. In addition,the present disclosure may repeat reference numerals and/or letters inthe various examples. This repetition is for the purpose of simplicityand clarity and does not in itself dictate a relationship between thevarious embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper,” “vertical,” “horizontal,” and the like, may be usedherein for ease of description to describe one element or feature'srelationship to another element(s) or feature(s) as illustrated in theFigures. The spatially relative terms are intended to encompassdifferent orientations of the device in use or operation in addition tothe orientation depicted in the Figures. The apparatus and structuresmay be otherwise oriented (rotated by, for example, 90°, 180°, ormirrored about a horizontal or vertical axis) and the spatially relativedescriptors used herein may likewise be interpreted accordingly.

The structures and methods detailed below relate generally to thestructures, designs, and manufacturing methods for IC devices, includingfin field effect transistor (FinFET) devices. Although the structuresand methods will be discussed in terms of FinFET devices, the structuresand methods are not so limited and are suitable for inclusion inmanufacturing processes for other classes of IC devices.

In FinFET devices, the mobility performance is influenced by both theepitaxial (EPI) volume and the associated device topography which, inturn, is dependent on the strained source drain (SSD) profile.Embodiments of the disclosed methods, by providing improved control ofthe SSD profile through control of the etch chamber conditions, willtend to reduce manufacturing defects while improving device mobility andperformance.

In particular, the deviations in the sizing of the photoresist (PR)post-etch openings as determined at the after etch inspection (AEI) areindicative of the likelihood and nature of associated defects. If thepost-etch photoresist (PR) opening is larger than the manufacturingtarget, there is an increased likelihood of over etch-related damage tothe device. Conversely, if the post-etch PR opening is smaller than themanufacturing target, there is an increased likelihood of incomplete orpartial etching defects. Further, in some current manufacturingprocesses, epitaxial (EPI) volume and topography control usually involveadjustments to the EPI deposition recipe in order to achieve a targetgrowth rate which, in turn, negatively affect the EPI tool productivityand/or the final EPI composition in some instances. Variations in thefinal EPI composition and configuration will tend to degrade and/orincrease the variability of the performance of the resulting IC device.

FIG. 1 is a cross-sectional view of an etching tool 100 useful in themanufacture of a FinFET device structure according to some embodiments.In some embodiments, the etching tool 100 comprises a chamber wall 102,which, in combination with a chamber lid 104, encloses a functionalchamber volume 106 into which the etchant(s) will be introduced. In someembodiments, the chamber lid 104 will include a heating apparatus 114for increasing the temperature of the chamber lid 104 above the ambienttemperature T_(a) or a base operating temperature T_(b) (when there isself-heating from the etch process that increases the temperature of thechamber lid 104 above the ambient temperature T_(a)) to reach a targetpolymerization temperature T_(p) range. In some embodiments, the chamberlid 104 includes a temperature sensor 116 for monitoring the temperatureof the chamber lid 104.

In some embodiments, the temperature sensor 116 will transfertemperature data to a controller 118 that will, in turn, control thepower applied to the heating apparatus 114 in order to maintain thetemperature of the chamber lid 104 within a predetermined temperaturerange. Although, as shown, in some embodiments the heating apparatus 114will be incorporated into the chamber lid 104 including, for example,resistive heating elements or channels through which a heated workingfluid is forced and at least one temperature sensor for generating asignal used by a controller for controlling the additional heatingprovided by the heating apparatus. In other embodiments the heatingapparatus 114 will be provided on the lower surface of the chamber lid104 or at other positions within the functional chamber volume 106,including, for example radiant heating elements, resistive heatingelements, or tubing through which a heated working fluid is forced, andat least one temperature sensor for generating a signal used by acontroller for controlling the additional heating provided by theheating apparatus. The heating apparatus 114 is positioned in order toapply radiant heating to the surface of the wafer 110 and the etchpattern 112 provided on the wafer 110. Similarly, although as shown, insome embodiments the temperature sensor 116 will be incorporated intothe chamber lid 104, in some other embodiments the temperature sensor116 (or sensors) will be positioned within the functional chamber volume106 in order to monitor the temperature of the chamber lid 104 and/orthe amount of radiant heating being applied to the surface of the wafer110 and the etch pattern 112 provided thereon.

In some embodiments a wafer support 108 is arranged and configured tohold a wafer 110 within the functional chamber volume 106 of etchingtool 100 during the etching process. Additional mechanisms including,for example, tracks, stages, elevators, arms, and/or guides (not shown)usable for removing the wafer 110 from a carrier or track (not shown)and positioning the wafer 110 on the wafer support 108 are included. Thesame or other additional mechanisms including, for example, tracks,stages, elevators, arms, and/or guides (not shown) usable after the etchprocess has been completed for removing the wafer from the wafer support108 and transferring the wafer 110 to a carrier (not shown), track, orother transport apparatus for movement to the next step in themanufacturing process are included.

During the etching process, one or more etchant species are introducedinto the functional chamber volume 106 as a plasma or other activatedspecies and applied to the exposed surfaces of the wafer 110. In someembodiments, the etchant will include one or more halogen compoundsincluding, for example, CF₄, Cl₂, and/or HBr, that will remove thematerial or materials on the wafer 110 that are exposed by etch pattern112. In addition to removing material from the exposed surfaces, theetchant(s) will also interact with the materials used to form the etchpattern 112. In some embodiments, when photoresist (PR) is used informing a portion of the etch pattern 112, the interaction with theetchant(s) will product polymeric compounds of varying stoichiometrywhich can be represented by the formula C—H_(x)—F_(x) (in which F is oneor more halogen species).

FIGS. 2A and 2B are cross-sectional views of a FinFET structure at anintermediate step in the manufacture of a FinFET device. The FinFETstructures 200A and 200B, in which the cross-sectional views are offsetby 90°, each include a substrate 202, a fin structure 204, a strainedsource/drain (SSD) recess 206, fin sidewalls 208, an etch mask 210, anetch stop layer 212, e.g., silicon nitride (SiN), polysilicon 214, andsidewalls 216. FIGS. 2A and 2B represent a FinFET structure that hasbeen manufactured without the benefit of the embodiments of the methodsand structures disclosed below.

FIGS. 3A and 3B are cross-sectional views of a FinFET structure at anintermediate step in the manufacture of a FinFET device. The FinFETstructures 300A and 300B, in which the cross-sectional views are offsetby 90°, each include a substrate 302, a fin structure 304, a strainedsource/drain (SSD) recess 306, fin sidewalls 308, an etch mask 310, anetch stop layer 312, e.g., silicon nitride (SiN), polysilicon 314, andsidewalls 316. FIGS. 3A and 3B represent a FinFET structure that hasbeen manufactured with full benefit of the embodiments of the methodsand structures disclosed below.

In some embodiments, the temperature of the chamber lid 104 is increasedabove a base operating temperature T_(b) (the chamber lid temperatureresulting from performing the etch process without supplemental heatingof the chamber lid) to a polymerizing temperature T_(p) at which thepolymeric compounds represented by the formula C—H_(x)—F_(x) (in which Fis one or more halogen species) will be preferentially or increasinglydeposited on the more horizontal surfaces of wafer 110 to form polymericdeposits 318 as the etch process progresses. In some embodiments, thesepolymeric deposits 318, will be found on the exposed surface of thestrained source/drain (SSD) recess 306, the upper surfaces of the finsidewalls 308, the etch mask 310, and the upper surfaces of thesidewalls 316. Without being bound by theory, the inventors believe thatthese polymeric deposits 318 provide additional protection to theexposed surface of the strained source/drain (SSD) recess 306 and theetch mask 310 during the etch process, thereby suppressing over-etch andundercutting modalities.

The temperature difference between the base operating temperature T_(b)and the polymerizing temperature T_(p) will vary as a function offactors including, for example, one or more of the plasma etchchemistry, the plasma energy, the reactor pressure, the photoresistcomposition and thickness, and the correlation between the increasedtemperature of the heat source, e.g., the reactor chamber lid and/orsupplemental heating elements, and the temperature increase at the uppersurface of the wafer. In some embodiments, reactor chamber lidtemperature increases of, for example, as little as 3 to 5° C. aresufficient to induce increased polymer formation and to suppress polyetch pattern erosion and thereby reducing etch damage to sensitivestructures. In other embodiments, the temperature difference between thebase operating temperature T_(b) and the higher polymerizing temperatureT_(p) will be greater than 5° C. in order to induce a degree ofpolymerization sufficient to suppress poly etch pattern erosion andbetter maintain the patterned dimensions, and thereby reduceetch-induced damage to structures protected by the poly etch pattern.

With respect to the exposed surface of the strained source/drain (SSD)recess 306, the additional protection provided by the polymeric deposits318 formed in some embodiments reduces both the width and depth of thestrained source/drain (SSD) recess 306. With respect to the etch mask310, the additional protection provided by the polymeric deposits 318formed in some embodiments reduces the etch-induced erosion of the etchmask 310 and reduces the width of the resulting pattern opening, therebyimproving the dimensional performance, improving etch mask 310 sidewallretention, and decreasing the likelihood of etch-induced damage, toimprove both the width and depth of the strained source/drain (SSD)recess 306.

FIGS. 4A and 4B are cross-sectional views of a FinFET structure at anintermediate step in the manufacture of a FinFET device. The FinFETstructure 400A corresponds to FinFET structure 200A in FIG. 2A after afirst EPI structure 418 a is formed to fill a lower portion of SSDrecess 206 after which a second EPI structure 420 a is formed. Structure400B corresponds to FinFET structure 300A in FIG. 3A after a first EPIstructure 418 b is formed to fill a lower portion of SSD recess 306after which a second EPI structure 420 b is formed. Each of thestructures 400A and 400B include a substrate 402, a fin structure 404,and first 418 a, 418 b and second 420 a, 420 b EPI structures grown fromthe exposed surfaces of the strained source/drain (SSD) recesses 206,306 shown in FIGS. 2A and 3A, an etch pattern 410, an etch stop layer412, e.g., silicon nitride (SiN), polysilicon 414, and sidewalls 416.

FIG. 4A is a FinFET structure 400A that has been manufactured withoutthe benefit of the embodiments of the methods and structures herein and,consequently, even using the same etch pattern 410 and etch process,tends to have a deeper strained source/drain (SSD) recess 206.Consequently, FinFET structure 400A has a second EPI structure 420 agrown from the first EPI structure 418 a which was grown from theexposed surfaces of the strained source/drain (SSD) recess 206 that islarger and has a less controlled geometry/topography.

FIG. 4B is a FinFET structure 400B that has been manufactured with fullbenefit of the embodiments of the methods and structures herein and,consequently, even using the same etch pattern 410 and etch process,tends to have a shallower strained source/drain (SSD) recess 306.Consequently, FinFET structure 400B has a second EPI structure 420 bgrown from the exposed surfaces of the first EPI structure 418 b thatwas grown from the exposed surfaces of strained source/drain (SSD)recess 306 that is smaller and has a more controlledgeometry/topography. This increased control of the etching process, andthe corresponding improvement in the EPI structure 420 b when comparedwith the EPI structure 420 a with respect to EPI volume andgeometry/topography, tends to improve both the manufacturing yield andperformance of finished IC devices manufactured according to someembodiments.

FIG. 5 is a cross-sectional view of a FinFET device structure 500 at anintermediate step of manufacturing having a lack of control of thedimension of the pattern opening according to some embodiments. As shownin FIG. 5 , the structure 500 includes a substrate 502, a fin structure504, a bottom layer (BL) 514, an EPI structure 520 grown from theexposed surfaces of the strained source/drain (SSD) recesses 206, 306shown in FIGS. 2A and 3A. As also shown in FIG. 5 , the structure 500includes an etch mask 510, that exposes a portion of a top surface ofthe BL 514, which is then etched to form opening 522, with a residualportion of the BL 514 protecting the EPI structure 520 during the etchprocess.

FIG. 5 also indicates a first opening sidewall profile 524 obtainedusing some embodiments in which the sidewall overetch is suppressed toreduce the likelihood that the EPI structure will be affected by theetch process. FIG. 5 also indicates, with a dashed line, a potentialsecond opening sidewall 526 profile that would result from excessivesidewall etch resulting from undercutting of the etch mask 510 duringthe etch process which produces a wider opening 522. If the etch mask510 is undercut, the wider opening tends to reduce or eliminate theportion of the BL 514 that is protecting the EPI structure 520. The lossof this covering will lead to the exposure, or near exposure, of aportion of the EPI structure 520, thereby exposing the EPI structure 520to damage at a region 528. Damage to the region 528 of the EPI structure520 results from the diffused or direct exposure of the region 528 toincreasing levels of the etchant gases as the protective portions ofbottom layer 514 matter are removed from first opening sidewall profile524 during the etch process.

As illustrated in FIGS. 3A and 3B, the polymeric deposits 318 reduce theerosion of the etch mask 310, 510 and reduce the etch-induced increasein the dimensions of opening 522. When the etch-induced erosion of theetch mask 310, 510 causes an increase in the dimensions of the opening,the thickness of the pattern material protecting other structures isreduced, increasing the likelihood that the etchant will damage orotherwise degrade such structure. When such etch damage occurs, themanufacturing yield, performance, and/or the reliability of theresulting IC devices will be compromised. Accordingly, protecting thepattern dimensions and maintaining the pattern opening dimensions forthe duration of the etch process will tend to improve the manufacturingyield, performance, and/or the reliability of the resulting IC devices.

FIG. 6 is a cross-sectional view of a FinFET device structure 600according to some embodiments with certain dimensions marked. Inparticular, monitored dimensions include the Proximity (the offsetbetween the poly 614 sidewall and the sidewall of the recess 606measured at the surface (S), the tip (T) (measured 27 nm below thesurface/reference plane (or about 50% of the total depth)), and thebottom (B) (measured 43 nm below the surface/reference plane (or about80% of the total depth to provide improved repeatability in themeasurement)). Other monitored dimensions include the dummy sidewall(DSW) thickness 616 w, the hard mask (HM) height 610 h, the fin sidewall(FSW) height 529 h (FIG. 5 ), the strained source drain (SSD) Depth:spacing ratio, 606 d: 623 w, Proximity (T) measured in input/output (IO)regions, the photoresist (PR) opening 522 (FIG. 5 ), the strained sourcedrain (SSD) Depth 606 ds (in SRAM regions), the EPI Height 624 h, andthe EPI Depth 625 h and the Total EPI (624 h+625 h) and 520 h (FIG. 5 ).

Departures from the target values for these dimensions will tend todegrade the yield, performance, and/or reliability for the resulting ICdevices. RO Recess Depth values that are above or below the targetvalues are associated with reduced manufacturing yields. Proximityvalues that are above or below the target values are associated withreduced manufacturing yields and values below the target values areassociated with reduced breakdown voltage (V_(BD)) performance. DSW andHM values that are above or below the target values are associated withdisrupted epi growth and reduced epi quality. FSW values that are aboveor below the target values are associated with reduced dimensionalcontrol of the subsequent epi deposition. Variations in the depth:spacing ratio(s) are also associated with increased device performancevariability.

In some embodiments, when manufacturing N7 node FinFET devices using anSSD process, a range of target parameters are used for achieving thepredetermined dimensions. The 7 nm foundry node utilizes a variety ofpatterning technologies including one or more selected from pitchsplitting, self-aligned patterning, and EUV lithography. Each of thesetechnologies is capable of being used for providing critical dimension(CD) control and pattern placement for producing the corresponding ICdevices. Pitch splitting involves splitting (or separating) patternfeatures that are too close together to pattern consistently ontodifferent masks with the plurality of masks then being exposedsequentially. Accurate alignment of the plurality of masks and theconsistency of the exposure provide the necessary CD control across themultiple exposures.

Representative dimensions for certain of the structures and structuralrelationships are provided below in Table 1.

TABLE 1 MTS Element/Dimension NSSD PSSD Ref Nos. RO Recess Depth 59 nm56 nm 606dr (in the RO region) Proximity (S) 7 nm 7 nm S: 630w (at RefPlane) Proximity (T) 7 nm 3 nm T: 631w (27 nm below Ref Plane) Proximity(B) 9 nm 9 nm B: 632w (43 nm below Ref Plane) DSW CD 7 nm 7 nm 616w HMHT >50 nm >50 nm 610h FSW Height 12.5 nm 12.5 nm 529h SSD Depth/Spacing<1:1 <1:1 623w:606ds Ratio IO Proximity (T) >10 nm >9 nm Proximity (T)in IO region PR Opening Width (nm) Target-1.5 nm 522w SSD Depth 50-52 nm606ds (in the SRAM region) EPI Recess Height 5~6 nm 624h EPI Depth30.5~31.5 nm 625h Total EPI 35.5~37.5 nm 520h

By utilizing embodiments of the disclosed method, a number ofimprovements are obtained over the standard poly etch processingincluding, for example, increased control over the width of the openingformed in the poly etch mask (specifically the photoresist portion)indicating the reduced pattern undercut experienced when polymericdeposits formed on the exposed surfaces of the poly etch pattern, e.g.,silicon oxide/photoresist, that results in a smaller opening extendingthrough the polysilicon. According to some embodiments, the SSD depthhas improved control, thereby reducing the risk of defects associatedwith over-etched and/or enlarged strained source/drain (SSD) recess 306regions that will tend to complicate and/or degrade the subsequent EPIgrowth process. Further, by better controlling the SSD recess depth, thesubsequent EPI growth process can more quickly fill the enlargedstrained source/drain (SSD) recess.

FIG. 7 is a flowchart of a method 700 of manufacturing an IC deviceaccording to some embodiments of the method that comprise a sequentialseries of operations including an optional operation 702 involving theidentification of poly etch patterns that have tight or challengingmargins and/or spacing using an IC layout design. At operation 704, awafer bearing a poly etch pattern, e.g., see FIGS. 3A and 4B, is loadedinto the etch reactor chamber. At operation 706, the temperature and, insome embodiments, one or more other process conditions, e.g., plasmaenergy, plasma flowrate, chamber pressure, etchant gas mixture, are setin a manner that will promote formation and deposition of one or morepolymeric species on the exposed surfaces of the wafer, e.g., see FIG. 1.

At operation 708, after the predetermined process conditions have beenobtained, the wafer is etched to remove at least a portion of thepolysilicon/silicon material exposed by the poly etch pattern, e.g., seeFIG. 3A, recess 306. At operation 710, the remainder of themanufacturing operations are performed to obtain a functional IC device,including, for example, epitaxial growth of a first layer ofsemiconductor material, e.g., see FIG. 6, 620 p, followed by theepitaxial growth if a second semiconductor structure, e.g., see FIG. 4A,420 . Additional operations include the deposition, patterning, andetching of a plurality of metal layer patterns (not shown), theinterlayer dielectric (ILD) materials that separate the metal patterns,and the via and/or contact openings provided through the ILD layers thatprovide for predetermined electrical connections between the variousmetal patterns. Depending on the purpose and configuration of thefunctional IC device, at optional operation 712 the IC device can beprogrammed. At optional operation 714, the completed (and optionallyprogrammed) IC device is subjected to a functional test, to evaluateoperation of the IC device according to IC design parameterscorresponding to the device under test (DUT) including, for example,function, speed, and reliability, and packaged (and/or packaged and thentested) before delivery to a customer.

FIG. 8 is a block diagram of an electronic process control (EPC) system800, in accordance with some embodiments. Methods used for generatingcell layout diagrams corresponding to some embodiments of the FinFETstructures detailed above, particularly with respect to the addition andplacement of the field plate contact on the RPO structure areimplementable, for example, using EPC system 800, in accordance withsome embodiments of such systems. In some embodiments, EPC system 800 isa general purpose computing device including a hardware processor 802and a non-transitory, computer-readable, storage medium 804.Computer-readable storage medium 804, amongst other things, is encodedwith, i.e., stores, computer program code (or instructions) 806, i.e., aset of executable instructions. Execution of computer program code 806by hardware processor 802 represents (at least in part) an EPC toolwhich implements a portion or all of, e.g., the methods described hereinin accordance with one or more (hereinafter, the noted processes and/ormethods).

Hardware processor 802 is electrically coupled to computer-readablestorage medium 804 via a bus 818. Hardware processor 802 is alsoelectrically coupled to an I/O interface 812 by bus 818. A networkinterface 814 is also electrically connected to hardware processor 802via bus 818. Network interface 814 is connected to a network 816, sothat hardware processor 802 and computer-readable storage medium 804 arecapable of connecting to external elements via network 816. Hardwareprocessor 802 is configured to execute computer program code 806 encodedin computer-readable storage medium 804 in order to cause EPC system 800to be usable for performing a portion or all of the noted processesand/or methods. In one or more embodiments, hardware processor 802 is acentral processing unit (CPU), a multi-processor, a distributedprocessing system, an application specific integrated circuit (ASIC),and/or a suitable processing unit.

In one or more embodiments, computer-readable storage medium 804 is anelectronic, magnetic, optical, electromagnetic, infrared, and/or asemiconductor system (or apparatus or device). For example,computer-readable storage medium 804 includes a semiconductor orsolid-state memory, a magnetic tape, a removable computer diskette, arandom access memory (RAM), a read-only memory (ROM), a rigid magneticdisk, and/or an optical disk. In one or more embodiments using opticaldisks, computer-readable storage medium 804 includes a compact disk-readonly memory (CD-ROM), a compact disk-read/write (CD-R/W), and/or adigital video disc (DVD).

In one or more embodiments, computer-readable storage medium 804 storescomputer program code 806 configured to cause the EPC system 800 (wheresuch execution represents (at least in part) the EPC tool) to be usablefor performing a portion or all of the noted processes and/or methods.In one or more embodiments, computer-readable storage medium 804 alsostores information which facilitates performing a portion or all of thenoted processes and/or methods. In one or more embodiments,computer-readable storage medium 804 stores process control data 808including, in some embodiments, control algorithms, process variablesand constants, target ranges, set points, programming control data, andcode for enabling statistical process control (SPC) and/or modelpredictive control (MPC) based control of the various processes.

EPC system 800 includes I/O interface 812. I/O interface 812 is coupledto external circuitry. In one or more embodiments, I/O interface 812includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen,and/or cursor direction keys for communicating information and commandsto hardware processor 802.

EPC system 800 also includes network interface 814 coupled to hardwareprocessor 802. Network interface 814 allows EPC system 800 tocommunicate with network 816, to which one or more other computersystems are connected. Network interface 814 includes wireless networkinterfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wirednetwork interfaces such as ETHERNET, USB, or IEEE-1364. In one or moreembodiments, a portion or all of noted processes and/or methods, isimplemented in two or more EPC systems 800.

EPC system 800 is configured to send information to and receiveinformation from fabrication tools 820 that include one or more of ionimplant tools, etching tools, deposition tools, coating tools, rinsingtools, cleaning tools, chemical-mechanical planarizing (CMP) tools,testing tools, inspection tools, transport system tools, and thermalprocessing tools that will perform a predetermined series ofmanufacturing operations to produce the desired integrated circuitdevices. The information includes one or more types selected fromoperational data, parametric data, test data, and functional data usedfor controlling, monitoring, and/or evaluating the execution, progress,and/or completion of the specific manufacturing process. The processtool information is stored in and/or retrieved from computer-readablemedium 804.

EPC system 800 is configured to receive information through I/Ointerface 812. The information received through I/O interface 812includes one or more of instructions, data, programming data, designrules that specify, e.g., layer thicknesses, spacing distances,structure and layer resistivity, and feature sizes, process performancehistories, target ranges, set points, and/or other parameters forprocessing by hardware processor 802. The information is transferred tohardware processor 802 via bus 818. EPC system 800 is configured toreceive information related to a user interface (UI) through I/Ointerface 812. The information is stored in computer-readable medium 804as user interface (UI) 810.

In some embodiments, a portion or all of the noted processes and/ormethods is implemented as a standalone software application forexecution by a processor. In some embodiments, a portion or all of thenoted processes and/or methods is implemented as a software applicationthat is a part of an additional software application. In someembodiments, a portion or all of the noted processes and/or methods isimplemented as a plug-in to a software application. In some embodiments,at least one of the noted processes and/or methods is implemented as asoftware application that is a portion of an EPC tool. In someembodiments, a portion or all of the noted processes and/or methods isimplemented as a software application that is used by EPC system 800.

In some embodiments, the processes are realized as functions of aprogram stored in a non-transitory computer readable recording medium.Examples of a non-transitory computer readable recording medium include,but are not limited to, external/removable and/or internal/built-instorage or memory unit, e.g., one or more of an optical disk, such as aDVD, a magnetic disk, such as a hard disk, a semiconductor memory, suchas a ROM, a RAM, a memory card, and the like.

FIG. 9 is a block diagram of an integrated circuit (IC) manufacturingsystem 900, and an IC manufacturing flow associated therewith, inaccordance with some embodiments for manufacturing IC devices thatincorporate the improved control over the SSD and EPI profile. In someembodiments, based on a layout diagram, at least one of (A) one or moresemiconductor masks or (B) at least one component in a layer of asemiconductor integrated circuit is fabricated using manufacturingsystem 900.

In FIG. 9 , IC manufacturing system 900 includes entities, such as adesign house 920, a mask house 930, and an IC manufacturer/fabricator(“fab”) 950, that interact with one another in the design, development,and manufacturing cycles and/or services related to manufacturing an ICdevice 960. Once the manufacturing process has been completed to form aplurality of IC devices on a wafer, the wafer is sent to backend or backend of line (BEOL) for, depending on the device, programming, electricaltesting, and packaging in order to obtain the final IC device products.The entities in manufacturing system 900 are connected by acommunications network. In some embodiments, the communications networkis a single network. In some embodiments, the communications network isa variety of different networks, such as an intranet and the Internet.

The communications network includes wired and/or wireless communicationchannels. Each entity interacts with one or more of the other entitiesand provides services to and/or receives services from one or more ofthe other entities. In some embodiments, two or more of design house920, mask house 930, and IC Fab 950 is owned by a single larger company.In some embodiments, two or more of design house 920, mask house 930,and IC Fab 950 coexist in a common facility and use common resources.

Design house (or design team) 920 generates an IC design layout diagram922. IC design layout diagram 922 includes various geometrical patternsdesigned for an IC device 960. The geometrical patterns correspond topatterns of metal, oxide, or semiconductor layers that make up thevarious components of IC device 960 to be fabricated. The various layerscombine to form various IC features.

For example, a portion of IC design layout diagram 922 includes variousIC features, such as an active region, gate electrode, source and drain,metal lines or vias of an interlayer interconnection, and openings forbonding pads, to be formed in a semiconductor substrate (such as asilicon wafer) and various material layers disposed on the semiconductorsubstrate. Design house 920 implements a proper design procedure to formIC design layout diagram 922. The design procedure includes one or moreof logic design, physical design or place and route. IC design layoutdiagram 922 is presented in one or more data files having information ofthe geometrical patterns. For example, IC design layout diagram 922 canbe expressed in a GDSII file format or DFII file format.

Whereas the pattern of a modified IC design layout diagram is adjustedby an appropriate method in order to, for example, reduce parasiticcapacitance of the integrated circuit as compared to an unmodified ICdesign layout diagram, the modified IC design layout diagram reflectsthe results of changing positions of conductive line in the layoutdiagram, and, in some embodiments, inserting to the IC design layoutdiagram, features associated with capacitive isolation structures tofurther reduce parasitic capacitance, as compared to IC structureshaving the modified IC design layout diagram without features forforming capacitive isolation structures located therein.

Mask house 930 includes mask data preparation 932 and mask fabrication944. Mask house 930 uses IC design layout diagram 922 to manufacture oneor more masks 945 to be used for fabricating the various layers of ICdevice 960 according to IC design layout diagram 922. Mask house 930performs mask data preparation 932, where IC design layout diagram 922is translated into a representative data file (“RDF”). Mask datapreparation 932 provides the RDF to mask fabrication 944. Maskfabrication 944 includes a mask writer. A mask writer converts the RDFto an image on a substrate, such as a mask (reticle) 945 or asemiconductor wafer 953. The IC design layout diagram 922 is manipulatedby mask data preparation 932 to comply with particular characteristicsof the mask writer and/or requirements of IC Fab 950. In FIG. 9 , maskdata preparation 932 and mask fabrication 944 are illustrated asseparate elements. In some embodiments, mask data preparation 932 andmask fabrication 944 can be collectively referred to as mask datapreparation.

In some embodiments, mask data preparation 932 includes opticalproximity correction (OPC) which uses lithography enhancement techniquesto compensate for image errors, such as those that can arise fromdiffraction, interference, other process effects and the like. OPCadjusts IC design layout diagram 922. In some embodiments, mask datapreparation 932 includes further resolution enhancement techniques(RET), such as off-axis illumination, sub-resolution assist features,phase-shifting masks, other suitable techniques, and the like orcombinations thereof. In some embodiments, inverse lithographytechnology (ILT) is also used, which treats OPC as an inverse imagingproblem.

In some embodiments, mask data preparation 932 includes a mask rulechecker (MRC) that checks the IC design layout diagram 922 that hasundergone processes in OPC with a set of mask creation rules whichcontain certain geometric and/or connectivity restrictions to ensuresufficient margins, to account for variability in semiconductormanufacturing processes, and the like. In some embodiments, the MRCmodifies the IC design layout diagram 922 to compensate for limitationsduring mask fabrication 944, which may undo part of the modificationsperformed by OPC in order to meet mask creation rules.

In some embodiments, mask data preparation 932 includes lithographyprocess checking (LPC) that simulates processing that will beimplemented by IC Fab 950 to fabricate IC device 960. LPC simulates thisprocessing based on IC design layout diagram 922 to create a simulatedmanufactured device, such as IC device 960. The processing parameters inLPC simulation can include parameters associated with various processesof the IC manufacturing cycle, parameters associated with tools used formanufacturing the IC, and/or other aspects of the manufacturing process.LPC takes into account various factors, such as aerial image contrast,depth of focus (“DOF”), mask error enhancement factor (“MEEF”), othersuitable factors, and the like or combinations thereof. In someembodiments, after a simulated manufactured device has been created byLPC, if the simulated device is not close enough in shape to satisfydesign rules, OPC and/or MRC are be repeated to further refine IC designlayout diagram 922.

It should be understood that the above description of mask datapreparation 932 has been simplified for the purposes of clarity. In someembodiments, mask data preparation 932 includes additional features suchas a logic operation (LOP) to modify the IC design layout diagram 922according to manufacturing rules. Additionally, the processes applied toIC design layout diagram 922 during mask data preparation 932 may beexecuted in a variety of different orders.

After mask data preparation 932 and during mask fabrication 944, a mask945 or a group of masks 945 are fabricated based on the modified ICdesign layout diagram 922. In some embodiments, mask fabrication 944includes performing one or more lithographic exposures based on ICdesign layout diagram 922. In some embodiments, an electron-beam(e-beam) or a mechanism of multiple e-beams is used to form a pattern ona mask (photomask or reticle) 945 based on the modified IC design layoutdiagram 922. Mask 945 can be formed in various technologies. In someembodiments, mask 945 is formed using binary technology. In someembodiments, a mask pattern includes opaque regions and transparentregions. A radiation beam, such as an ultraviolet (UV) beam, used toexpose the image sensitive material layer (e.g., photoresist) which hasbeen coated on a wafer, is blocked by the opaque region and transmitsthrough the transparent regions. In one example, a binary mask versionof mask 945 includes a transparent substrate (e.g., fused quartz) and anopaque material (e.g., chromium) coated in the opaque regions of thebinary mask.

In another example, mask 945 is formed using a phase shift technology.In a phase shift mask (PSM) version of mask 945, various features in thepattern formed on the phase shift mask are configured to have properphase difference to enhance the resolution and imaging quality. Invarious examples, the phase shift mask can be attenuated PSM oralternating PSM. The mask(s) generated by mask fabrication 944 is usedin a variety of processes. For example, such a mask(s) is used in an ionimplantation process to form various doped regions in semiconductorwafer 953, in an etching process to form various etching regions insemiconductor wafer 953, and/or in other suitable processes.

IC Fab 950 includes wafer fabrication 952. IC Fab 950 is an ICfabrication business that includes one or more manufacturing facilitiesfor the fabrication of a variety of different IC products. In someembodiments, IC Fab 950 is a semiconductor foundry. For example, theremay be a manufacturing facility for the front end fabrication of aplurality of IC products (front-end-of-line (FEOL) fabrication), while asecond manufacturing facility may provide the back end fabrication forthe interconnection and packaging of the IC products (back-end-of-line(BEOL) fabrication), and a third manufacturing facility may provideother services for the foundry business.

Wafer fabrication 952 includes forming a patterned layer of maskmaterial formed on a semiconductor substrate is made of a mask materialthat includes one or more layers of photoresist, polyimide, siliconoxide, silicon nitride (e.g., Si₃N₄, SiON, SiC, SiOC), or combinationsthereof. In some embodiments, masks 945 include a single layer of maskmaterial. In some embodiments, a mask 945 includes multiple layers ofmask materials.

In some embodiments, the mask material is patterned by exposure to anillumination source. In some embodiments, the illumination source is anelectron beam source. In some embodiments, the illumination source is alamp that emits light. In some embodiments, the light is ultravioletlight. In some embodiments, the light is visible light. In someembodiments, the light is infrared light. In some embodiments, theillumination source emits a combination of different (UV, visible,and/or infrared) light.

Subsequent to mask patterning operations, areas not covered by the mask,e.g., fins in open areas of the pattern, are etched to modify adimension of one or more structures within the exposed area(s). In someembodiments, the etching is performed with plasma etching, or with aliquid chemical etch solution, according to some embodiments. Thechemistry of the liquid chemical etch solution includes one or more ofetchants such as citric acid (C₆H₈O₇), hydrogen peroxide (H₂O₂), nitricacid (HNO₃), sulfuric acid (H₂SO₄), hydrochloric acid (HCl), acetic acid(CH₃CO₂H), hydrofluoric acid (HF), buffered hydrofluoric acid (BHF),phosphoric acid (H₃PO₄), ammonium fluoride (NH₄F) potassium hydroxide(KOH), ethylenediamine pyrocatechol (EDP), TMAH (tetramethylammoniumhydroxide), or a combination thereof.

In some embodiments, the etching process is a dry-etch or plasma etchprocess. Plasma etching of a substrate material is performed usinghalogen-containing reactive gasses excited by an electromagnetic fieldto dissociate into ions. Reactive or etchant gases include, for example,CF₄, SF₆, NF₃, Cl₂, CCl₂F₂, SiCl₄, BCl₂, or a combination thereof,although other semiconductor-material etchant gases are also envisionedwithin the scope of the present disclosure. Ions are accelerated tostrike exposed material by alternating electromagnetic fields or byfixed bias according to methods of plasma etching that are known in theart.

In some embodiments, etching processes include presenting the exposedstructures in the functional area(s) in an oxygen-containing atmosphereto oxidize an outer portion of the exposed structures, followed by achemical trimming process such as plasma-etching or liquid chemicaletching, as described above, to remove the oxidized material and leavebehind a modified structure. In some embodiments, oxidation followed bychemical trimming is performed to provide greater dimensionalselectivity to the exposed material and to reduce a likelihood ofaccidental material removal during a manufacturing process. In someembodiments, the exposed structures may include the fin structures ofFin Field Effect Transistors (FinFET) with the fins being embedded in adielectric support medium covering the sides of the fins. In someembodiments, the exposed portions of the fins of the functional area aretop surfaces and sides of the fins that are above a top surface of thedielectric support medium, where the top surface of the dielectricsupport medium has been recessed to a level below the top surface of thefins, but still covering a lower portion of the sides of the fins.

IC Fab 950 uses mask(s) 945 fabricated by mask house 930 to fabricate ICdevice 960. Thus, IC Fab 950 at least indirectly uses IC design layoutdiagram 922 to fabricate IC device 960. In some embodiments,semiconductor wafer 953 is fabricated by IC Fab 950 using mask(s) 945 toform IC device 960. In some embodiments, the IC fabrication includesperforming one or more lithographic exposures based at least indirectlyon IC design layout diagram 922. Semiconductor wafer 953 includes asilicon substrate or other proper substrate having material layersformed thereon. Semiconductor wafer 953 further includes one or more ofvarious doped regions, dielectric features, multilevel interconnects,and the like (formed at subsequent manufacturing steps).

Thus, IC Fab 950 at least indirectly uses IC design layout diagram 922to fabricate IC device 960. In some embodiments, semiconductor wafer 953is fabricated by IC Fab 950 using mask(s) 945 to form IC device 960. Insome embodiments, the IC fabrication includes performing one or morelithographic exposures based at least indirectly on IC design layoutdiagram 922. Semiconductor wafer 953 includes a silicon substrate orother proper substrate having material layers formed thereon.Semiconductor wafer 953 further includes one or more of various dopedregions, dielectric features, multilevel interconnects, and the like(formed at subsequent manufacturing steps).

Details regarding an integrated circuit (IC) manufacturing system (e.g.,manufacturing system 900 of FIG. 9 ), and an IC manufacturing flowassociated therewith are found, e.g., in U.S. Pat. No. 9,256,709,granted Feb. 9, 2016, U.S. Pre-Grant Publication No. 20150278429,published Oct. 1, 2015, U.S. Pre-Grant Publication No. 20140040838,published Feb. 6, 2014, and U.S. Pat. No. 7,260,442, granted Aug. 21,2007, each of which are hereby incorporated, in their entireties, byreference.

FIG. 10 illustrates an etch process according to some embodiments of themethod. A wafer is loaded into an etch reactor chamber at an ambienttemperature T_(a), e.g., the room temperature of the fabrication area,LOAD, and heated RAMP1, to a nominal etch temperature T_(n), at whichpoint a first portion of etch process ETCH is initiated. At the nominaletch temperature, the deposition rate for polymerization products ontoan upper surface of the wafer DR₁, is relatively low. The temperaturewithin the etch reactor chamber is then increased to a polymerizationtemperature T_(p) RAMP2 in order to increase the deposition rate ofpolymerization products onto an upper surface of the wafer DR₂ during atleast a portion of the etch process, with DR₂>>DR₁. The additionalpolymerization products induced by etching at the polymerizationtemperature T_(p) aid in the control of critical dimensions for thestructures being etched into the upper surface of the wafer and tend toreduce the likelihood of damage to existing structures. Once the etchprocess has been completed, the wafer is cooled to near ambienttemperature RAMP3 before being discharged for the next manufacturingoperation UNLOAD.

Methods for manufacturing an integrated circuit according to someembodiments include loading a wafer having a polysilicon etch patterninto a reactor chamber, exposing the wafer to an activated etchantwithin the reactor chamber for a first portion of an etch period toremove polysilicon and form a recess under a nominal reactor temperatureT_(n), the nominal reactor temperature inducing a first polymericdeposition rate DR₁ on an upper surface of the wafer, and heating thereactor chamber to establish a polymerization temperature T_(p) withinthe reactor chamber during a second portion of the etch period, thepolymerization temperature inducing an increased second polymericdeposition rate DR₂ on the upper surface of the wafer, wherein DR₂ isgreater than DR₁.

Methods for manufacturing an integrated circuit according to otherembodiments include one or more additional operations including, forexample, forming the activated etchant from the group of etchant gasescontaining at least one halogen atom, forming the activated etchant fromthe group of etchant gases consisting of CF₄, Cl₂, HBr, and mixturesthereof, heating a reactor chamber lid to establish the polymerizationtemperature T_(p) within the reactor chamber, establishing thepolymerization temperature T_(p) of at least 3° C. above a base reactorchamber lid operating temperature T_(b), establishing the polymerizationtemperature T_(p) at least 5° C. above a base reactor chamber lidoperating temperature T_(b), growing a first epitaxial semiconductor onan exposed surface of the epitaxial recess and growing a secondepitaxial semiconductor on an exposed surface of the first epitaxialsemiconductor, setting the polymerization temperature T_(p) at least 5°C. above a base radiant heating assembly operating temperature T_(bR)and/or setting the polymerization temperature using radiant heating froma radiant heating assembly located within the reactor chamber.

Methods for manufacturing an integrated circuit according to someembodiments include retrieving an IC design layout diagram from a memorydevice, analyzing the IC design layout diagram for a poly etch spacingbelow a target value, and modifying a wafer fabrication process toinclude an enhanced poly etch process for IC design layout diagrams inwhich the poly etch spacing is below the target value, with the enhancedpoly etch process including the operations of exposing the wafer to anactivated etchant within the reactor chamber for a first portion of anetch cycle to remove polysilicon and form a recess under a nominalreactor temperature T_(n), the nominal reactor temperature inducing afirst polymeric deposition rate DR₁ on an upper surface of the wafer,and heating the reactor chamber to establish a polymerizationtemperature T_(p) within the reactor chamber during a second portion ofthe etch cycle, the polymerization temperature inducing an increasedsecond polymeric deposition rate DR₂ on the upper surface of the wafer,wherein DR₂ is at least 200% of DR₁.

Methods for manufacturing an integrated circuit according to otherembodiments include one or more additional operations including, forexample, selecting an etchant gas from the group of etchant gasesconsisting of CF₄, Cl₂, HBr, and mixtures thereof, heating a reactorchamber lid to a polymerization temperature T_(p) and thereby establishthe temperature condition within the reactor chamber, setting thepolymerization temperature T_(p) at least 5° C. above a base reactorchamber lid operating temperature T_(b), measuring the polymerizationtemperature T_(p) at a central region of the reactor chamber lid, and/orusing an embodiment of the method to manufacture a FinFET device.

Systems for manufacturing an integrated circuit according to someembodiments include a first deposition apparatus arranged and configuredfor depositing sidewall material adjacent a polysilicon structure on anupper surface of a wafer, a first etch apparatus arranged and configuredfor etching the sidewall material to form a sidewall adjacent thepolysilicon structure, a first coating apparatus arranged and configuredfor depositing a photosensitive material over the polysilicon structureand the sidewall, a first patterning apparatus arranged and configuredfor exposing a predetermined portions of the photosensitive material, afirst developing apparatus arranged and configured for removing aportion of the photosensitive material to form a poly etch pattern onthe photosensitive material and thereby expose a portion of thepolysilicon structure, a first etching apparatus arranged and configuredfor etching the exposed portion of the polysilicon structure, theduration of the etching being sufficient to remove a portion of theexposed polysilicon structure and form an epitaxial recess in the wafer,and a temperature controlled etch chamber lid provided on the firstetching apparatus for establishing and maintaining an elevatedpolymerization temperature within an etch chamber during a portion ofthe etching and thereby increase a polymer deposition rate on thesurface of the wafer.

Systems for manufacturing an integrated circuit according to some otherembodiments incorporate one or more additional elements including, forexample, a first epitaxial deposition apparatus arranged and configuredfor growing a first epitaxial semiconductor structure from a surface ofthe epitaxial recess; a first etching apparatus arranged and configuredfor utilizing an etchant gas selected from the group of etchant gasesconsisting of CF₄, Cl₂, HBr, and mixtures thereof, a deposition controlapparatus associated with the first epitaxial deposition apparatus, thedeposition control apparatus being arranged and configured forestablishing a ratio between a depth of the first epitaxialsemiconductor structure and an epitaxial recess height of less than apredetermined value, e.g., less than 6, and/or a second epitaxialdeposition apparatus arranged and configured for establishing growing asecond epitaxial semiconductor structure from a surface of the firstepitaxial semiconductor structure.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

1. A system for manufacturing an integrated circuit device comprising: areactor chamber configured for etching a wafer; a gas supply apparatusconfigured for introducing an etchant gas into the reactor chamber andmaintaining a predetermined processing pressure; a heating apparatusconfigured for heating the reactor chamber to a nominal reactortemperature T_(n) during a first portion of an etch period, wherein thenominal reactor temperature induces a first polymeric deposition rateDR₁ on an upper surface of the wafer; and heating the reactor chamber toa polymerization temperature T_(p) during a second portion of the etchperiod, wherein the polymerization temperature induces a secondpolymeric deposition rate DR₂ on the upper surface of the wafer andwherein DR₂ is greater than DR₁.
 2. The system according to claim 1,wherein: the gas supply apparatus is configured for introducing at leastone gas containing at least one halogen atom.
 3. The system according toclaim 1 further comprising: the gas supply apparatus configured forintroducing at least one gas selected from the group consisting of CF₄,Cl₂, and HBr.
 4. The system according to claim 1, wherein: the heatingapparatus is further configured for selectively heating a reactorchamber lid assembly when heating the reactor chamber.
 5. heatingapparatus configured according to claim 4, wherein: the heatingapparatus is configured for establishing and maintaining a reactorchamber lid polymerization temperature T_(L) that is at least 3° C.above a reactor chamber lid base operating temperature T_(b).
 6. Thesystem according to claim 4, further comprising: the heating apparatusis configured for establishing and maintaining a reactor chamber lidpolymerization temperature T_(L) that is at least 5° C. above a reactorchamber lid base operating temperature T_(b).
 7. The system according toclaim 1, further comprising: an epitaxial deposition apparatusconfigured for growing a first epitaxial semiconductor material on anexposed surface of the wafer; and growing a second epitaxialsemiconductor on an exposed surface of the first epitaxial semiconductormaterial.
 8. The system according to claim 4, wherein: the heatingapparatus comprises a radiant heating assembly within the reactorchamber.
 9. The system according to claim 7, wherein: the radiantheating assembly is configured for establishing the polymerizationtemperature T_(p) within the reactor chamber.
 10. A system formanufacturing an integrated circuit comprising: a memory deviceconfigured for maintaining an IC design layout; a processor configuredfor retrieving the IC design layout from the memory device; analyzingthe IC design layout for a region in which a poly etch spacing is lessthan a predetermined target spacing value; and in response to a polyetch spacing that is less than the predetermined target spacing value,modifying a wafer fabrication process to include an enhanced poly etchprocess; a plasma etch apparatus configured for receiving and etching aseries of semiconductor wafers in a reactor chamber; a gas supplyapparatus configured for introducing an etchant gas into the reactorchamber at a predetermined processing pressure; a power supply apparatusconfigured for supplying energy to the etchant gas sufficient to converta portion of the etchant gas within the reactor chamber to a plasma; aheating apparatus configured for heating the reactor chamber to anominal reactor temperature during a first portion of an etch processand induce a first polymeric deposition rate DR₁ within the reactorchamber; heating the reactor chamber to a polymerization temperatureduring a second portion of the etch period and induce a second polymericdeposition rate DR₂ on the upper surface of the wafer and wherein DR₂ isgreater than DR₁.
 11. The system according to claim 10, wherein: the gassupply apparatus is further configured for formulating the etchant gasfrom the group of etchant gases consisting of CF₄, Cl₂, HBr, andmixtures thereof.
 12. The system according to claim 10, wherein: theheating apparatus is further configured for selectively heating areactor chamber lid to a polymerization temperature T_(p).
 13. Thesystem according to claim 12, wherein: the heating apparatus is furtherconfigured for selectively heating a reactor chamber lid from a reactorchamber lid base operating temperature T_(b) to the polymerizationtemperature T_(p), wherein the polymerization temperature T_(p) is atleast 5° C. greater than the reactor chamber lid base operatingtemperature T_(b).
 14. The system according to claim 12, furthercomprising: a temperature measuring apparatus configured for measuring acurrent temperature of a central region of the reactor chamber lid. 15.The system according to claim 10, wherein: the heating apparatus isfurther configured and operated whereby the second polymeric depositionrate DR₂ is at least 200% of the first polymeric deposition rate DR₁.16. A system for manufacturing an integrated circuit comprising: a firstdeposition apparatus configured for depositing sidewall materialadjacent a polysilicon structure on an upper surface of a wafer; a firstetch apparatus configured for etching the sidewall material to form asidewall adjacent the poly silicon structure; a first coating apparatusconfigured for depositing a photosensitive material over the polysiliconstructure and the sidewall; a first patterning apparatus configured forexposing a predetermined portions of the photosensitive material; afirst developing apparatus configured for removing a portion of thephotosensitive material to form a poly etch pattern on thephotosensitive material and thereby expose a portion of the polysiliconstructure; a first etching apparatus configured for etching the exposedportion of the polysilicon structure, the duration of the etching beingsufficient to remove a portion of the exposed polysilicon structure andform an epitaxial recess in the wafer; and a temperature controlledchamber lid on the first etching apparatus for establishing andmaintaining an elevated polymerization temperature within an etchchamber during a portion of the etching and thereby increase a polymerdeposition rate.
 17. The system for manufacturing an integrated circuitaccording to claim 16, further comprising: a first epitaxial depositionapparatus configured for growing a first epitaxial semiconductorstructure from a surface of the epitaxial recess.
 18. The system formanufacturing an integrated circuit according to claim 16, wherein: thefirst etching apparatus is configured for utilizing an etchant gasselected from the group consisting of CF₄, Cl₂, HBr, and mixturesthereof.
 19. The system for manufacturing an integrated circuitaccording to claim 17, wherein: the first epitaxial deposition apparatusfurther comprises a deposition control apparatus configured forestablishing a ratio between a depth of the first epitaxialsemiconductor structure and an epitaxial recess height is less than 6.20. The system for manufacturing an integrated circuit according toclaim 17, further comprising: a second epitaxial deposition apparatusconfigured for establishing growing a second epitaxial semiconductorstructure from a surface of the first epitaxial semiconductor structure.